The present invention relates to an apparatus with context switching capability. Most embedded and real time control systems are designed according to a model in which interrupt handlers and software managed tasks are each considered to be executing on their own virtual microcontroller. That model is generally supported by the services of a real time executive or operating system, layered on top of the features and capabilities of the underlying machine architecture. A virtual microcontroller can be seen as a task having its own general purpose registers and associated special function registers like program counter, program status word, etc., which represent the task""s context. Handling of these virtual microcontrollers in most of the known systems is done by means of software which saves and restores the respective context. Therefore, software for such a data processing unit needs an increased amount of memory and execution overhead for the context switching operation reduces the processing bandwidth available to application tasks.
In general a context switch requires that the content of at least certain registers of a register file are stored in a predefined memory area and are replaced with the content of another memory area. Each memory area thereby represents a specific context which contains all necessary data related to a specific task or interrupt service routine. This operation, also called context switching, is a critical time consuming part within a so called real time operating system software. Such an operating system often has the object to react as quickly as possible on external or internal events.
It is an object of the present invention to provide a method and a data processing unit with the capability of fast hardware-assisted context switching, resulting in accelerated execution of context switching operations. This object is achieved by a data processing unit, comprising at least one register having at least one read port and one write port. The register has at least two memory cells each having a write line and a read line, a first switch comprises inputs and one output for coupling said read line of one of said memory cells with said read port, a second switch for coupling said write line of one of said memory cells with said write port is provided.
Another object of the present invention is to provide a method for fast context switching operations. This object is achieved by using at least one register comprising at least two memory cells, and a switch for read/write access of one of the memory cells in a data processing unit executing instructions stored in a memory unit. The method comprises the steps of: selecting a first memory cell in said register, upon execution of a first predetermined event, such as a instruction or exception, switching from said first memory cell in said register to another memory cell in said register, upon execution of a second predetermined event, switching back to said first memory cell.
A context switch occurs either by any call- or return-instruction, execution of an interrupt or trap or similar events. A context can consist of the content of a set of registers. A context can be divided into several parts, for example, into two parts, an upper and a lower context. In such a case it is in most cases only necessary to save one part forming the basic context. But, certain more complex routines might need to save more than a basic context. For these instances, special instructions provide the ability to save/restore the other parts of a context. Throughout the application context can mean both, the basic part of a context or the complete context.
Basically, the present invention provides a mechanism of automatically saving and restoring such a context which under most favorable conditions does not need any transfers of register contents from or to the memory. Each register which stores part of a context contains two or more memory cells. Instead of saving and restoring the content of each register the present invention provides a switching unit which switches between the different memory cells in each register in an appropriate way. In other words, each context is assigned to a different memory cell in the respective registers.
A less hardware intensive embodiment saves and restores only a fraction of registers which are assigned to a context, thus cutting down the number of execution cycles involved with each call- or return-instruction.
A register file having dual-bit registers according to the present invention has the advantage of allowing calls and returns to issue in parallel with integer pipeline operations. The invention can be applied to all kinds of microprocessors or microcontrollers. For example, microprocessors using a stack for call/returns or linked lists benefit from the present invention. Statistically, most calls return without further calls to another subroutine. In these cases a call or a return instruction only needs a minimum amount of cycles compared to a plurality of cycles which is needed to save all necessary registers in the prior art.
Further to the above portions of this section, which summarize embodiments of the present invention, the remainder of this section summarizes other embodiments, but not all embodiments.
According to one embodiment of the present invention, there is a method of context switching from a first task to a second task in a data processing unit having a memory and a plurality of registers coupled with the memory with a set of registers representing a context. Each of the registers has at least two memory cells and a selector to switch between the memory cells. The method includes: upon execution of a first predetermined event the step of speculatively storing a less than full portion of a current context from the set of registers to the memory and then switching to the next available memory cell in each of the registers, and upon execution of a second predetermined event the step of switching back to the previous memory cell in each of the registers.
According to another embodiment of the present invention, there is a method of context switching from a first task to a second task in a data processing unit having a memory and registers coupled with the memory with a set of registers representing a context, each of the registers having at least two memory cells, each memory cell having at least one read port and one write port and a switch to select one of the read ports and a switch for random access of the write ports. The method comprises: upon execution of a first predetermined event the step of speculatively loading at least a portion of a context into the plurality of registers from the memory and then switching to the read ports of the next available memory cell in each of the registers, and upon execution of a second predetermined event the step of switching back to the read ports of the previous memory cell in each of the registers.
According to another embodiment of the present invention, there is a method of context switching from a first task to a second task in a data processing unit having a memory and registers coupled with the memory with a set of registers representing a context, each of the registers having at least two memory cells, each memory cell having at least one read port and one write port and a switch to select one of the read ports and a switch for random access of the write ports. The method includes: upon execution of a first predetermined event the step of switching to the read ports of the next available memory cell in each of the registers, upon execution of a second predetermined event the step of switching back to the read ports of the previous memory cell in each of the registers, and upon execution of the first predetermined event and before switching to the read port of another memory cell the step of storing the content of the current memory cells of a predefined number of registers of the set of registers in the memory.
According to another embodiment of the present invention, there is a data processing unit that includes: at least one register having at least one read port and one write port, the register having at least two memory cells each having a write line and a read line, a first switch comprising inputs and one output for coupling the read line of one of the memory cells with the read port, a second switch having at least one input and outputs for coupling the write line of one of the memory cells with the write port, and a control unit configured to operate at least the first and second switches to, in response to a call instruction, speculatively initiate saving of content of current memory cells and select a next one of the at least two memory cells as the new current memory cell, wherein the new current memory cell is made available for use only after some content of the previous memory cells has been speculatively saved, and to, in response to a return event, select the previous memory cell as once again the current memory cell.
According to another embodiment of the present invention, there is a data processing unit that includes: a register file having a first set of registers and a second set of registers, the registers in the first set of registers having at least one read port and one write port and the registers each having n memory cells each having a write line and a read line, wherein n is at least two, a first switch for coupling a read line of one of the memory cells of each register of the first register set with a respective read port, and a second switch for coupling a write line of one of the memory cells of each register of the first register set with a respective write port, a memory, a bus that couples the first set of registers with the memory, wherein the bus is configured to transfer a context from the first set of registers to the memory in p cycles, and a control unit that controls the switches to conduct context switching, including speculatively saving contexts to memory that may not ultimately need to be saved to memory so that even if n calls are executed without intervening returns, the calls are guaranteed to take less than p cycles each.